1. Field of the Invention
The present invention relates to a method of forming a flash memory cell and more particularly to a method of manufacturing a flash memory cell capable of preventing a loss of charges injected into a floating gate thereof.
2. Description of the Prior Art
A principle of data write operation in a flash memory device is to make a program/erase status by applying an appropriate voltage to a source, a drain and a control gate and then charging or discharging electrons to a floating gate, applying an appropriate voltage to a source, a drain and a control gate.
FIG. 1 is a cross-sectional view showing a method of manufacturing a conventional flash memory cell, especially, a stack gate flash memory cell.
A gate oxide layer 11 is formed on a semiconductor substrate 10, and a polysilicon layer 12 for a floating gate is formed on an entire structure. Then, a patterning process is performed to form the floating gate. Sequentially, a dielectric layer 13 and a polysilicon layer 14 for a control gate are formed on the entire structure. Then, the dielectric layer 13 and the polysilicon layer 14 are patterned by a self-alignment etching process, thereby forming a control gate 14. Next, a source region S and a drain region D are formed by performing an ion implantation process.
In a program operation of the stack gate flash memory cell, voltages of 9 V and 5 V are applied to the control gate terminal Vg and the drain terminal Vd, respectively. If such voltages are applied, a channel pinch-off phenomenon occurs at the drain, and electrons injected at the source S obtains an energy by moving along a surface channel and passing through a high electric field adjacent to the drain D. Some of hot electrons which are formed by the obtained energy pass beyond a potential barrier and are injected into the floating gate 12. On the contrary, in an erase operation, voltages of -9 V and 4.3 V are applied to the control gate terminal Vg and the source terminal Vs, respectively. If such voltages are applied, F-N tunneling occurs toward the gate oxide layer 11 of the source which is overlapped with the floating gate, so that the electrons charged in the floating gate 12 are leaked out.
A most important factor determining a reliability of the stack gate flash memory device is data loss fail. That is, the electrons injected into the floating gate leak through various paths to an exterior due to various stimulus such as time, temperature, external bias and the like, so that an original program status is not maintained and the data is lost. Additionally, among the paths, the electron-outflow toward the gate oxide layer of the source is very serious, and therefore, the reliability of the device is degraded.